ZSNES board

Have you tried that with BPL/BMI instead of BGE/BLT?

root@anomie# cat /proc/cpuinfo processor : 0 vendor_id : AuthenticAMD cpu family : 5 model : 7 model name : AMD-K6tm w/ multimedia extensions stepping : 0 cpu MHz : 299.614 cache size : 64 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 1 wp : y...

One thing to note, on 4d it sounds like you're saying that DoTransfer should always be set to true when NTLRx is loaded... and above you mention that dotransfer is always false when starting mid-frame. That would suggest that writing to $420c would clear DoTransfer. That, or DoTransfer is cleared a...

I've seen the operand "#\1" used in some macro code for loading VRAM using DMA in the SNES programming wikibook . These come up numerous times, and I'm not sure what they're doing with those. Macro arguements, most likely. would it be possible to write text to the screen without making pa...

Here's what I have noted as the process the SNES follows for each line's HDMA transfer. Note that the 'DoTransfer' flag is always initially false when starting a transfer mid-frame. 1. If DoTransfer is false, skip to step 3. 2. For the number of bytes (1, 2, or 4) required for this Transfer Mode... ...

mozz wrote:I know writing docs is a tedious, time-consuming task.

For me, it's more that i have to pay the bills. Which doesn't leave much time for the extensive testing and double-verification that writing a good doc requires...

byuusan wrote:

(3) What would it take to get anomie and byuu together to produce one heavenly volume of SNES technical documentation goodness?

A salary would be nice.

Seconded.

However, the algorithms described for DAA/DAS in the Intel instruction set reference doc appear to be completely equivalent to Overload's (as long as the x86 Auxiliary-carry flag and Carry flag are set to the SPC's H flag and C flag before the DAA/DAS is executed). Try A=0xFA to 0xFF (with ch clear...

Palette data is stored in CGRAM, which is accessed via PPU2 Registers $2121, $2122, and $213B. CGRAM is 256 15-bit words. All colors are stored in BGR555 format. Thus, there is no place in ROM to find palettes, you have to look for writes to $2122 (note DMA and HDMA may be used for this prupose). OB...

But, when hackin up your own software there's no way to get around your hard coded vectors, is there? Directing them to a small interrupt handler in RAM is the way to go, obviously. You could stick RAM everywhere except the RESET vector, as long as you make sure to initialize the RAM before using t...

It's worth of note that the interrupt vectors all reside in ROM space, so you can't change them in run-time. Not necessarily, the cart could put whatever it wants there. For example, the SA-1 allows certain of those vectors to be altered. If you enable the feature in a particular SA-1 register, the...

I'd be surprised if it would work, simply because of the way the thing works. The gun watches the TV screen looking for the electron beam, and signals the SNES when it sees it. From the timing of the "I see it!" signal, the SNES can know where the gun is pointing. Connecting the gun to a c...

There is one exception: When $4210 bit 7 is read when V==225/240 && HC==2 (e.g. the first possible cycle where $4210 bit 7 *CAN* be set), the nmi_read flag is not set, even though $4210 bit 7 is set. Therefore, two reads in a row result in $4210 bit 7 being set. That's what I suspected... N...

Hmmm... I will update the test to write a counter for each test so I can determine if the $4210 bit 7 test is triggering twice. That makes a hell of a lot more sense, but it's still very strange. It seems to pass the second time at the start of $e2. Either the NMI interrupt handler eats almost exac...

See for yourself: http://byuu.org/files/nmi_timing.zip It looks more like the "latch when 44210 bit 7 set" test is sometimes passing twice... It may or may not be because you don't PHP/PLP in your NMI handler, and it may or may not be because of the oddity we've found where $4210 bit 7 is...

Like anomie said, there's ~5.5 dot delay after V=$4209, but this delay seems to magically disappear between 333-339, lest the IRQ would never trigger. It never bumps it to the next scanline as you'd expect. The exact delay changes every scanline. I get correct results ~90% of the time with a 5.5 do...

When you're coding an SNES game, are there standard interrupt vector types that SNES or ZSNES expects? Like are they actually required so that the ROM code will load up Well, you need to set the Reset vector to something sane, since the first thing the SNES does on power up is load the address at $...

So what's up with the horrible dot-clock distortion long after HDMA init, and before the first HDMA transfer? Where are your NOPs getting inserted, before or after the Init? It must be because HDMA is trying to align itself with new frames, and its 8-cycle clock is getting out of sync with the numb...

We always knew HDMA didn't terminate the DMA transfer, it just pauses it while the HDMA occurs. HDMA Init isn't supposed to be constant. It works much like DMA: it waits until the edge of a CPU cycle (but can be mid-opcode), 'syncs' to the DMA clock, does some work (8 per channel, plus another 16 pe...

But the flags aren't passing the last SNES test. anomie's document is very vague with when these flags are set. That's because we don't actually know exactly when they're set. But as you've surmised, they seem to be set at some point in the vicinity of the first scanline with a RO or a TO, and not ...

Wow, anomie: you're a genius. Your DMA timing notes are amazing. I was able to get exact emulation results to my SNES with all four possible DMA counter positions, with either a 6 or 8 cycle "next" opcode cycle time (nop vs lda $2137, second cycle being 6 or 8), and with any number of cha...

Well, as the DSP doc states, initial value is 0x4000, and on each iteration 'internal' is updated as your code does. The actual noise sample is exactly this internal, though. The noise sample replaces the BRR decoded sample, before volume adjustments or the 15-to-16 bit conversion. All this was dete...

A non-interlaced screen has the SAME data, shown twice for each frame. So can the emulator just output at 25 or 30 FPS and look fine? Sorry, that's not how it works. The SNES renders a frame at 50 or 60 Hz, and either outputs it all (standard non-interlace mode) or outputs only half of it (interlac...

Still don't understand this. I have the 6, 8, or 12. Now how do I turn that into 2-12? What do I subtract from the 6/8/12 to get that? You start the DMA transfer with 2-8 cycles, then add your overheads and your byte costs. Call the total of all this T. Then add 2-6, 2-8, or 2-12 cycles so T+x is a...

presumably so the data exposed between the two chips stays in sync always. Two portions of the same chip, actually... Now, we transfer all of the data, each byte taking 8 cycles. Plus 8 cycles overhead per channel, plus one more 8 cycles for the whole DMA. Now, once we're finished, you say that the...