ZSNES board

...I should add that if you encode speeds in a few bits of a lookup table you already have, then you have already paid for the cache miss. That might make it preferable to TRAC's method (I don't know). Even if that is possible, you may very well end up slowing down the use of the piggybacked LUT, w...

IIRC, DAA/DAS on x86 can have a 'double carry/borrow' into the high nybble for invalid values, and the 6502-family and SPC700 do not have that issue. Because of this, for accurate outputs of SPC700 DAA/DAS, x86 DAA/DAS is useless. Also, because of the differences in results, the flags are not the sa...

Overload, re: your SPC flag test program... I was trying to debug why it was freezing on SNEeSe, obviously a SNEeSe problem since it works MOST of the time on the real hardware, when I noticed a shortcoming in the test source. Sometimes, the test program seems to freeze on my SNES + copier. Most of ...

Just committed fixes to DAA and DAS opcodes to SNEeSe CVS, as well as BRK and RETI support. (which I suspect may be broken...) Also committed changes to DIV to use anomie's algorithm. DAA and DAS can both alter their behavior based on the H flag. I used a modified version of anomie's APU test progra...

How does the break flag affect xcn? I don't quite follow. The 'effect' was that if break flag is set before the test, then the test would fail, even if the test would pass if break flag was clear prior. Nothing in the XCN test (or any other) affects the break flag (on the stack or otherwise). That ...

Very good work, interesting test and interesting results. Unfortunately, the test has a shortcoming, which can be revealed by adding the bytes $0D $AE $08 $10 $2D $8E (push psw, pop a, or a,#$10, push a, pop psw) before the spc_xcn_test label and extending the test size appropriately ($7D). Combined...

anomie wrote:You're right, of the MOV ops, only MOV (X)+,A and MOV dd,ds don't read the dest. BTW, i don't seem to have a listing for a MOV (X), (Y) opcode. And MOVW d,YA only reads the low byte of dest.

Yeah, my bad. I've been going at this code too long, there is no MOV (X),(Y).

(edited for clarity) anomie, (re: SPC700) you mentioned that ADDW/SUBW set H flag on high byte; is Z flag set on high byte only also, or on the full result? Also, is Z flag set on the high byte only or the full result for INCW/DECW? Regarding registers FD-FF (timer counters) being reset on 'write'; ...

They agree, except for two things. For invalid headers, snes9x uses ~0x7FF, while SNEeSe uses ~0xFFF. And in the Method 2 and 3 filters, snes9x at one point uses "- (prev1 >> 1)" while SNEeSe uses "+ (-last2 >> 1)". Any comments? SNEeSe is incorrect on the invalid headers, will ...

More SPC700 info tonight. On reset, the SPC700 side of the IO registers ($00f4-7) does get reset. I set things up with ldx #$0200 stx $2142 stz $2141 lda #$cc sta $2140 stp And on reset $2140-1 were displaying $bbaa rather than what my code at $0200 would do. I recently did some tests that verified...

Yes, that's exactly what I was trying to say. I'm going to copy that ;) Hurrah! Also, about the 4-bit counter - do we know if it wraps around, or saturates? They wrap. This has been verified, then? Well, the 5A22's IRQ timer actually treats all dots on the scanline as 4 master cycles no matter what...

anomie wrote:

TRAC wrote:Have attempts been made to set IRQs for H=340? I can't seem to remember...

No IRQ will trigger for H=340.

Then.. one would expect that, while the latches report normal-length dots for the 'short' line on odd NI frames, the 5A22 still treats them as long dots?

-- edited many times - hopefully not again [8-May-2005 - 0252 - 0500 GMT] We can only examine the top level directly. If the middle level is cleared on disable or on enable, there's no observable difference if it doesn't increment while disabled. I suspect the bottom level runs constantly, and that ...

Combine this with the fact that estimates for the 'worst case' bandwidth requirements by the SDSP would require considerably more bandwidth than 1.024MB/s, upwards to twice that, and you start suspecting that another solution needs to be found. i'm not familiar with these estimates... For a given a...

A few opcodes at least are fairly obvious, for example it seems that it needs an IO cycle to do the +X in "d+X", but no IO cycle between the reads and writes in something like "ASL d". Branches take 2 extra cycles when successful (i'd guess it always does the equivalent of 65816...

Oh, and note that an IRQ set for (153,240) will not trigger on the short frame in non-interlace mode. And for some reason, an IRQ set for dot 153 on the last scanline of the frame (261, or 262 for interlace mode long frames) will not trigger. Perhaps the IRQ H-counter does not suffer from the 'mani...

The dev forum has been dead for a while. I wouldn't say tolerate, I'd say thanks for bringing it back to life! Indeed, Nach. Hurrah for byuusan, who is willing to ask questions, accept new information, and provide excuses for much info to be gathered and verified. Now if only I'd get around to veri...

On an NTSC SNES, we normally have scanlines 0-261, each with 340 dots but dots $143 and $147 are 1.5 times as long as the rest, for a total of 1364 (341 'dots') per scanline. Except line 240 ($f0) every other SNES-frame, which has $143 and $147 the normal length. Does this have any relation to $213...

I know it's one pixel out, but I assume that can occur when the cycle is not exact to the pixel (at least, I hope!). Yeah, it happens. Just keep in mind that the smallest discrete unit of measurement of CPU timing is half a dot (difference between slow and fast bus cycle length), so your results co...

I wasn't :O The 65816 pdf states that interrupts use: Opcode fetch (who knows what address this should be 6/8 cycles) IO (always 6 cycles) Stack write * 3/4 (unless your stack is at $2100, probably always SlowROM) Vector fetch * 2 (always SlowROM) Actually, hardware interrupts have 2 IO and soft in...

It is just an example instruction, and it's been more-or-less been followed through by example the later test byuu did. For each of the Fetch-decode-execute stages, the evaluated address (PBR/DBR:AAH:AAL) the data is fetched/stored to, dictates the number of machine cycles (either 6,8 or 12; depend...

It's not that weird, check out some of the later NES timing docs and you'll find it has the same quirk (except it always acts like interlace is off - because it doesn't support interlace, of course).

-TRAC

Compared to what I've seen for the Genesis, Gameboy, and Wonderswan Color, yes. I admit I haven't really looked at any other systems in much detail... The Genesis, for example, has one 68k official PDF, and two or three snippets of info from various hackers, which are pasted together in different o...

I was meaning to make more notes, and I forgot to even make these x.x There's a * (system base timing) and ** (PPU timing) that were to be referring to notes, and those notes are here. I meant to do more, but I'm TIRED. :( *'There are 341 dots per line, and 262 lines per frame.' Exceptions are descr...

Greetings, everyone. :) Nach suggested I visit here, and I'm quite glad that I did. As much as I might appreciate the praise by evilant, it appears I have a bit of a task ahead of me, in attempting to clean up as much of the misinformation that remains. :cry: I tried to go through the thread and men...