ZSNES board

In order to get DRAM refresh matching my SNES with the new cycle-by-cycle core, I actually had to make it occur mid-opcode. We figured that recently, IIRC. I tried to do the test again tonight, but unfortunately, it does not work after resetting the SNES. I just get a blank screen. I tried it ~10 t...

I know these don't match your results, this is probably because I'm now actually latching the counters at the exact cycle position they should be (as far as we know). Hrm... What position during the 6-cycle read are you latching, and what position during the 6-cycle read are you 'latching' the bits...

BTW, what's scratchpad ram? Probably $0000-$1fff in banks $00-$3f and $80-$bf... then see if $00:1000 mirrors $20:0000 I have $20:0000-1fff mapped to $00:0000-1fff... So that would mean $00:1000 = $20:1000, right? Err... yeah, typo. Sorry. No thoughts on why Open Bus doesn't work for me? I would pr...

My SNES+UFO pass the SNES Test Program electronics test, too; but I have no idea what all that tests. Ummm... i wrote this all down at one point. Let's see... The testing begins at ~$00:84b3 with something about scratchpad ram, then $2180-3 to read/write all RAM, then see if $00:1000 mirrors $20:00...

Ok, interesting news: it seems HDMA will interrupt an instruction mid-cycle to execute, no waiting until the end of the instruction. Ick. I set up a Byuu test ROM to HDMA frop open bus into $2180, and then I manually disable HDMA after the first scanline (when HDMA always runs). The code in the gene...

The CLI/RTI issue is most likely due to the pipelining done by the cpu. The flags register is probably updated during the opcode fetch for the next instruction. This means that it will be too late for it to affect IRQ handling until the next instruction is finished. Why would CLI/SEI allow an IRQ b...

I figured HDMA would wait until the current instruction had completed, like NMIs and IRQs. Probably... OTOH, i have a bit of a suspicion that for a "STA $420B ; NOP" the processor might just be paused for DMA after the opcode load but before the IO cycle, based on the open bus value. A lo...

On a side note, what is somebody with your skills doing in a labor intensive job? You have the programming ability, learning ability, and smarts to do better. I understand this can be a rather personal question, and we all have our reasons and problems, so you don't have to share if you don't want ...

By the way, I have some bad news: I just started working again, full-time, and as it's a rather dead-end laborious job, it's sapping all of my motivation and energy away. I'll try and work on things when I can, but expect to see a lot less from me for the next few months :( Ick, i know how that is...

Back from vacation/sickness now. Here's something interesting, discovered way back when. As you know, IRQ is level-triggered, so if you forget to read $4211 in your IRQ handler routine it'll re-trigger as soon as you clear the I flag (probably with your RTI). However, one game (Marko's Magic Footbal...

The only other problem would be that I might have to mask the (address + 1) on a few addressing types that wrap around the bank/page/whatever. I haven't really worked those out, need to read over the results you posted on that a while back. You have to watch out for other boundaries too, e.g. LDX $...

Actual tests. Set up the SNES at first power-on with: clc : xce : rep #$20 : pea $2100 : pld Now notice if you use lda $37, you get latch value n . Now if you use lda $2137, you get latch value n + 2 . If you use asl $2137, you also get latch value n + 2 . If you use lda $2136, you get latch value ...

The good news is that I figured out how the opcode cycles factor into the latch positions returned by $2137, the bad news is that it actually happens in the middle of the opcode. How did you figure this? Actual tests, or just theory? The fourth cycle is where $2137 is actually read. The counter is ...

Are any of those numbers verified at all? Like /RESET remaining high for 130 cycles, or the reset vector requiring 52 cycles? According to the datasheet, /RESET is 2 IO cycles, 3 stack access cycles, and 2 vector read cycles: 6+6+8+8+8+8+8 = 52. And it really isn't so much "/RESET stays high f...

Another quick test: If i LDA $2137 as the very first instruction, I latch dot 53.0 (cycle 212) after reset. Inserting NOPs and such to get to WRAM Refresh, the very first refresh is at 538. If we want to make the assumption that the WRAM Refresh 'counter' starts at the same time the reset pulse clea...

Are you sure we're getting accurate positions here? I was under the impression that we don't know how much the lda $2137 interferes with the resulting latch positions yet. You mean WRT an LDA $2137 LDA $4212 pair? As i said, i tested it directly by removing the LDA $2137, and the $4212 bits changed...

It could be that you wrote to CGRAM/whatever when the SNES wasn't in v/hblank or whatever and then STP locked the processor. That's what the WAI was supposed to be for... Anyway, the actual test doesn't take terribly long, and even if you do manage to cut it off early the numbers should still be go...

I tried to run your test on my UFO, but it didn't work. It works on my emulator, and the screen turns white when its done. But on my UFO, the screen says 'Testing in progress...' and that never goes away, even after half an hour. Hrm... looking at the SRAM, the test finished, but must have gotten s...

Tonight's results: i've written a version of Byuu's test so I can do some more experimentation. In particular, I've created a version that does a LDA $4212 right after the LDA $2137 and displays that value in addition to the latch position. It runs these LDAs in FastROM, so we can 'take out' the LDA...

Why would you suspect that? Doesn't seem to make sense to me why 240+241 would be the same. Dots 323/327 are way after the refresh, unless because line 240 starts at 538 and line 241 would be 534, but since the line was 4 dots short, line 241 starts at 538... hmmm. During most scanlines, it's eithe...

First off, I realized that we were both wrong about which dots have 6 master cycles. The correct dots are 322 and 326, sort of. It's really hard to explain, so take a look at the following table: Hrm.... on my SNES, i still get 323 and 327, constant. What results to you get from the test I sent you...

There's no way to tell where a 'wait until next frame' loop ends. Use the same loop you use to wait for the start of the first frame: - lda $4212 : bpl - : - lda $4212 : bmi -. If it's reliable to go to the start of the odd frame, shouldn't it be reliable enough to skip to the next even frame too? ...

My tests indicate that lda $002137 results in a higher value than lda $37. I'll try it again, though, to be sure. Send me your test too, so i can check on my SNES. As for interlace, I'm curious if the start position will always be 538 for even lines, and 534 for odd, or if the extra scanline will i...

The important part is the actual latching instruction. If the refresh pause is soft, a longer instruction (LDA $002137) would let us latch a later dot position than a shorter one (LDA $37) since the latch-read comes during the final 6 cycles of the instruction. Well, a test of mine gives the same r...

I guess this really doesn't matter too much, huh? Although checking for this would make a great regional lockout, I'm completely certain that emulating the correct dot based on system isn't neccesary. For the record, though. What versions are your 5c77/5c78? Which region/style SNES? 1 and 3 (and 2 ...