ZSNES board

Format: (cycle count:$213c dot position:nop opcode count) [...] 1310:326:647 Hmmm... my SNES gives dot 327 here, not dot 326. What are your 5c77 and 5c78 version numbers? I also beat the hell out of the dram refresh stuff again while I was at it. Now then, I am absolutely positive that DRAM refresh...

Awesome, so now all we need to do is figure out all the dot anomalies I've found that non-interlace dots $143 and $147 are 6 master cycles instead of 4. You've found that line 241 is short every other frame, so i'm sure that those two dots become normal then. That's it. Oh, and i've yet to get a cl...

If you make the frame count big enough, you won't even need the stopwatch ;) But i'd rather not spend all day running just one test ;) 35 minutes is long enough. Results: Non-interlace mode takes ~2129.981788 seconds to run 128000 frames. Interlace takes ~2133.850515. That's ~60.09 and ~59.98 fps. ...

More SPC700 results: i finally found a way to get the numbers to add up to match the results observed on my real SNES! But it's a rather interesting change: i have to simulate the SPC700 at ~1026900 Hz rather than 1024000 Hz (or decrease the 5A22 master clock to give the same ratio (or both)). Any t...

(b) Lease, Sale, or Other Transfer of Additional Copy or Adaptation. - Any exact copies prepared in accordance with the provisions of this section may be leased, sold, or otherwise transferred, along with the copy from which such copies were prepared , only as part of the lease, sale, or other tran...

DRAM Refresh is, without a doubt, exactly 40 master cycles (10 dots) long. It occurs on every scanline at the same position regardless of interlace/frame #. How do you figure this? I can't think of any dot-latching test results that would work with 40 master cycles and 1364 master cycles per scanli...

More APU timing results: the 64KHz timer ticks every 16 SPC700 cycles, and no 'refresh' or anything was detected. But is it really 64 KHz? The problem so far: in a normal frame, the SPC700 should execute on average (1365*262-2)/(1.89e9/88)*1024000 ~= 17051.1 cycles. OTOH, we can only account for 131...

I'll recreate the test ROM and post it here tomorrow, but I'm pretty sure that I do. I have to reset once of course since the copier doesn't jump in at exactly the right point. Run the test for multiple frames too, if you haven't been... I typically sample and write the value to the screen every fr...

Best bet, IMO: set up an IRQ far away from NMI, fastrom, SEI and WAI for it, and LDA $37. Hope you latch a stable value (i.e. always latch line 100 dot 42). Then SEI and WAI again, but this time insert 1767 NOPs before the LDA $37. If I'm correct, 1324 would latch H+5 while 1325 would latch only H+...

If I read $2140 every NMI, the separation is 0x522 or 0x523 in non-interlace mode, and 0x527 or 0x528 for the long frames in interlace mode. More info: it's all right about 50-50, with maybe a slight bias one way or the other. However, when the SNES is 'cold' it's less stable and only gets to 50-50...

But what would we time against? Just the $213c latch. If the refresh is 41 cycles, with 9 dots of 4 cycles and one of 5 cycles, that adds to exactly 10 dots. If the refresh is 40 cycles with all 10 dots 4 cycles, that adds to exactly 10 dots. Then we could use a combination of opcodes that would be...

I did a test a month or two ago to determine which horizontal counter values could not be latched and the results showed that only 8 pixels could not be latched (OPHCT: 135-142, $87 - $8E). I tested on both my PAL and NTSC systems. Current theory is that the refresh waits until completion of the cu...

SPC700 timing experiments: All involve loading this program into the SCP700, then looking at the output of $2140: .DB $e8, $00 ; 0200: MOV A,#$00 .DB $8d, $00 ; 0202: MOV Y,#$00 .DB $8f, $00, $01 ; 0204: MOV $00, $01 .DB $8f, $01, $00 ; 0207: MOV $01, $00 .DB $7a, $00 ; 020a: ADDW YA,$00 .DB $da, $f...

I like that theory. It would be difficult, but we could probably time an exact cycle count from the WRAM refresh if we ran enough tests similar to your lda $37/$3c/$3c/sta $80 loop and averaged the results. But what would we time against? I really wish we knew what WRAM refresh was... maybe it's re...

Is it possible the SNES just locks the processor during the extra scanline? I mean, we don't "see" the WRAM refresh period in our tests at all. We only notice it because it's right in the middle. What if there is synchronization between scanlines, or between frames, or both? There's not a...

Let's throw a few more numbers into the mix. I've run a test to measure the number of master cycles executed between NMIs, and a test to measure basically the length of a dot. The frame length test (time between NMIs) records 0x70dd or 0x70de iterations of the fastrom 'INY' instruction (12 master cy...

Statistical analysis. The idea is, if i latch semi-randomly several thousand times (i believe the total ended up over 14 million) then all dots of the same length should get about the same number of latches. If a dot is 1.5 times as long as the rest, it should tend to get 1.5 times the number of lat...

Hrm, let's see how well I understand this. On an NTSC SNES, we normally have scanlines 0-261, each with 340 dots but dots $143 and $147 are 1.5 times as long as the rest, for a total of 1364 (341 'dots') per scanline. Except line 240 ($f0) every other SNES-frame, which has $143 and $147 the normal l...

anomie wrote:Absolute Indexed Indirect -- (a,X): Adding X will wrap within bank 0. No info on wrapping for the address read again, same reason.

Ok, i'm dumb. (a,X) uses the PBR, not bank 0 like (a). So (a,X) will wrap within the PB bank, and address loads will similarly wrap within the bank.

It'll be quicker to list the ones I know about. $2100 can be written any time. If you disable force-blank mid scanline, you get graphics glitches for a few tiles (and OBJ probably for the rest of the scanline). $2102, $2103, $2104, and $2138 may be accessed any time. However, the behavior will not b...

I've run some tests, to attempt to confirm the address wrapping behavior described in the datasheet. First, the PC does wrap. If an opcode spans the boundary (e.g. a 2-byte opcode begins at $xx:FFFF), that will wrap within the current bank as well. Absolute mode -- a: Word reads (in native mode) wil...

There can definately be a place for platform-specific emulators, and for platforms with mmap of fine enough granularity that would be a good technique. snes9x uses something much like the table thing, although $4000-$41ff is just special cased in the read routine to add an extra 6 cycles and the blo...

FYI, i'm working on fixing snes9x's timing. We already have/attempt the different memory access speeds. At the moment, though, we don't even have the right lengths for all opcodes under all conditions. OTOH, not too long ago we didn't have timing for HDMA either until I tested it on the SNES. snes9x...

Yeah, it happens. Just keep in mind that the smallest discrete unit of measurement of CPU timing is half a dot (difference between slow and fast bus cycle length), so your results could be half a dot off either way. Hence, a minimum of two tests, carefully designed to ensure that one starts at an e...

I've recently run a test and discovered that at least some writes do affect the Open Bus value. In particular, I set up a test rom with a 'LDA #$6B / STA $DB' at $1ffc, so the following opcode would be read from open bus. And the SNES didn't halt, so the $6B must have taken effect. I also found that...