ZSNES board

I've never actually seen inline do what it's supposed to. Every time I examine the assembly generated, it's always still a function call. But I compared the routine with and without inline, and the former seemed a tad bit faster, so just for the purpose of the demonstration app, I left it in. I've ...

I have before me a spec for standard C written when C++ was standardized in 98 which says no inline for C. MSVC I believe also does not support inline in C. I don't care what MSVC does. I'm looking at this draft, referenced from here . You sure all compilers support it? I know GCC removed the old t...

You can only inline in C++ which is fine since that's what you seem to be defining the file as. Hrm, the copy of the C (not C++) draft standard I'm looking at right now tells me that inline is valid in C, and suggests that the function be inlined... Setting void however as the parameter while fine ...

Yay, more dev topics! (: I'm trying to come up with a way to synchronize the SNES main clock (315/88*6mhz) with the APU clock (~1.024mhz) down to individual cycles of each clock -- I plan to emulate each at the cycle level for fun. I'm thinking we'll have to do the 5A22 at the cycle level to get DMA...

Does the real SNES support Hi-Res Mode 7, or is it an emulation enhancement? That depends on what you mean by "hi-res Mode 7". It is possible to enable pseudo-hires (via register $2133, SETINI) on Mode 7, and with EXTBG and some creative palettizing you could even get a halfway decent dis...

My problem is just that with all the newly emulated features requiring new variables, I have to find some way to pull those out of old savestates and guess/recalculate what value they should have. Major pain. I can't say I care about trying to write things so old versions can use new states though, ...

We're not gonna add new chip tests at the end and write bad code just so that snes9x can still load our states. And we wouldn't want you to, if i may speak for snes9x. snes9x's savestates need a major overhaul too, BTW. The annoying part is keeping the ability to load old snes9x savestates in overh...

I don't think people should need autoconf on their system whether they are compiling from CVS, or from cvs snapshots put together by ipher. Most projects using autoconf require autoconf when compiling from CVS. There's not much point in having automatically generated files cluttering up your CVS ch...

http://www.sonicspot.com/guide/synthesis.html - low pass filtering It also has a nice description of what ADSR is (as it is currently emulated in ZSNES) I don't know how it's implemented in ZSNES, but i didn't see anything in there that looked too much like the SNES's ADSR. OT: In the SNES: The vol...

Ack, we lost the DMA timing info! I guess i'll have to rewrite it... Anything else we're missing? It seems to me that the DMA timing involves two different clocks. First, once $420b is written the S-CPU has time to complete one more CPU cycle before pausing for DMA (typically, this is the opcode loa...

Edit: It'd be faster to replace c = (c << 3) | (int)(((float)c / 31.0 * 7.0)) with c = (c << 3) | (c >> 2)... but I use a color lookup table anyway, so it's a moot point. AFAIK, that's more or less 'standard'. In general, just repeat the high-order bits to fill the low order bits as needed.

The time I measured before the SSMP starts executing the IPL after reset seems to be ABOUT 5 SSMP instruction cycles (fractional component involved, plus inaccuracies due to async clocks causing communications variances). Only 5? hrm... Then, it is true that the ports are writable from the 5A22 sid...

More SPC700 info tonight. On reset, the SPC700 side of the IO registers ($00f4-7) does get reset. I set things up with ldx #$0200 stx $2142 stz $2141 lda #$cc sta $2140 stp And on reset $2140-1 were displaying $bbaa rather than what my code at $0200 would do. $00f1 bits 4 and 5 clear the ports whene...

I believe this is because the getenv() function in FreeBSD returns a memory address outside the ZSNES program memory store, so trying to free is means that it's trying to free memory it didn't create. Um... No. The problem is getenv() is simply not failing for you. Um... Not really. The problem is ...

This has been verified, then? The wrapping? Yes. I set up a wait loop that effectively counts down from ~0x100f0, with timer #2 set for a target of 1, and still no saturation. Hmm. It's just that I'm trying to find some reasoning for the 'no IRQ on H=339 on short scanline' case, and for both that a...

Do you mean them as the 3 stages of: Stage 1: 128:1 (T0, T1) or 16:1 (T2) scaler. Stage 2: 1-256 'divisor', based on a 0-255 wraparound counter and a post-increment comparator. Stage 3: The 4-bit counter for output ticks from the comparater stage. Yes, that's exactly what I was trying to say. I'm g...

To make sense of the SSMP opcode timings, I expect a 4.096MB/s rate equally shared would be sufficient. I don't see any way it could use 8.192MB/s with the SSMP timings and SDSP data we have. OTOH, 8.192 would be more than enough then. Maybe the DSP needs to run at that speed to do whatever it need...

Combine this with the fact that estimates for the 'worst case' bandwidth requirements by the SDSP would require considerably more bandwidth than 1.024MB/s, upwards to twice that, and you start suspecting that another solution needs to be found. i'm not familiar with these estimates... However, our ...

Have attempts been made to set IRQs for H=340? I can't seem to remember... :oops: No IRQ will trigger for H=340. any ideas on researching SPC700 bus timing software-side? You mean getting data along the lines of the GTE datasheet for the 65816? It should be _possible_ since S-CPU can access the IO ...

Division by zero actually gives results (seemingly Y=A and A=$FF-Y). Overflows by just 1 bit give sane results, but beyond that we start getting variations on the divide-by-zero "formula". Anyone have any ideas, before i try to figure it out? Ok, i think I have it. It's a fairly standard ...

I've finished with the SPC700 opcode timing, only the one instruction was wrong in the doc. Of course, I couldn't test STOP or SLEEP since both halt the processor (I suspect SLEEP == WAI, except there's no I to WA for). I've also begin testing the math instructions. Decimal arithmetic is rather easi...

The interesting thing was that I tested in Mode1 with interlace disabled and sprite interlacing enabled. I noticed absolutely no flickering that would be apparent if this were the case. I'll make a better test to confirm, though. I'll make every even horizontal line red, and every odd one green, an...

Nach wrote:One of the problems though is that some of the code is in a loop, and the goto jumps right into the middle of it :x

Well, on the one hand you can probably set things up so the FSM handles the loop: 0 -> 1 -> 2 -> back to 1. Or you could stick a Duff's Device in there.

I don't understand how the screen can be rendered non-interlace, and the sprite as interlaced. IIRC we tested this in the other thread. Recall that the SNES normally outputs only one field constantly. Interlace must be enabled on BGs as well as OBJ to properly render 'interlaced' even-and-odd with ...

... damnit. Oh well, I'm sure we'll notice the pattern eventually with lots of patience. The question is, why the variable delay in the first place? If we could figure that out, we'd probably be set... [later] SPC700 timing results: Remember way back when my "12-cycle" test looked like it...