ZSNES board

This, of course, isn't a problem if that code is running in RAM, but I don't really understand how to handle that yet. Just copy the relavent code into RAM and JML to it. You could use DMA something like this: rep #$10 ; set X and Y registers 16 bits sep #$20 ; set A register (and STZ) 8 bits ldx #...

I was looking at the mess known as dsp4emu.c/dsp4emu.cpp There's all these parts where the code sets a number, drops out for more data, then continues by gotoing a lable based on the number. I was thinking to clean up the code a bit it would be possible to just drop out and have the continue contin...

So far, I've tested this with SlowROM, and the 4-step delay pattern seems to be: { 24, 16, 16, 16 } Which fits, it's difficult to determine if the latch is X or X.5 when the delay can change drastically for a .5 dot difference in starting position... I just picked { 22, 16, 14, 16 } because that al...

I have a question regarding valid usage. I know normally longjmp() is valid if setjmp()'s surrounding function hasn't returned yet. But what if the function calling setjmp() was reentered in the same manner causing the stack to setjmp()'s function to be the same as it was before? But how do you kno...

OK, that's not a problem. Do you know if it's a real /RESET output - that is, it goes low when the cartridge is reset, and only then? The SNES-Kart documentation seems to suggest it goes low on every ROM access, which seems very bizarre... and makes it not a /RESET. I highly doubt it's weird like t...

I had figured that /RESET was a hard-reset line. I was also hoping there was a soft reset mechanism as well, but I haven't been able to find it. /RESET is a reset output. The only input comes from the switch on the front of the SNES. Otherwise, I need to figure out a way to start a cartridge after ...

What do you have as pin 54? It's /WE on most of the docs I've seen. It's what's connected to the /WE on SRAM. I have it as "/WR", sounds like the same thing. "Write" versus "Write Enable" or something like that. 1: Read from ROM address: /CART goes low, /OE goes low /W...

though I have one issue in that I don't know which SNES connector pad is /CS and which is /OE. I saw on fruity site (CR) that The Dumper mentioned that those two typically get reversed... in siudym's documentation, "/CE" goes to ROM /CE and RAM /OE, which seems wrong (that would be an /OE...

Looks like WDM is two memory access cycles. About as I expected. I just changed my standard test to insert WDMs instead of NOPS, and each gave an extra .5 dot ;) But as I've noticed on my NTSC TV, it doesn't actually show all the lines, it's just the visible image appears a little lower (hence the i...

Sounds interesting. Don't know how feasible, but interesting. 1) The SNES memory maps I have show the DSP, SuperFX, etc. as being at 0x3000-3FFF from banks 00-3F, but the DSP emulation page I found (http://users.tpg.com.au/trauma/dsp/dsp1.html) lists it as 00-1F:6000-7FFF in Mode 21, and 20-3F:8000-...

I don't know how the values change exactly when you perform a DMA/HDMA transfer. I've tested this now. DMA: $43x2-3 are incremented and $43x5-6 are decremented to 0. Nothing else changes. Direct HDMA: On init, first copy $43x2-3 into $43x8-9 (along with $43x4, this points to the current table index...

Anyone know what happens to SPC RAM during reset? IIRC, nothing. But the bootstrap routine clears and resets the stack, and the ROM must be re-enabled if it had been disabled. And probably the registers ($f1 and $f4-7, which includes $2140-7f on the S-CPU side) get reset. Feel free to correct me if...

But you have initialization delays for each active channel in HDMA, I was thinking those could probably vary like DMA does, in addition to all the other complexities of HDMA. The current numbers are "18" master cycles per scanline if any channels are still active, plus 16-56 cycles per ch...

I counter your yahoo page's claim of legality with Snopes!


Goodnight.

With LoROM, you can have FastROM or SloROM. This means that data accessed in $8x:xxxx banks and above run the SNES CPU at 3.58Mhz because ROM access is faster there. The SNES CPU runs in SloROM mode for ROM access below those locations and the SNES CPU runs at 2.68Mhz. HiROM, LoROM, or whatever has...

pagefault wrote:Both 9x and UO (UO is just a bunch of hacks and actually hardly emulates anything giving off the false appearance it's actually accurate, see source code) both of them use hacks to get this game working.

Hrm... i removed the hack from my branch of snes9x, and it still seems to work. Nifty.

or something I can do to fix it? Yes, implement Range/Time Over for zsnes. :D ??? The SNES can only display 32 sprites on any one scanline (range), and only 34 sprite-tiles (time). So if the game sticks 35 sprites on one line, only the first 32 will actually be displayed, the other 3 will not be dr...

Locke4382 wrote:or something I can do to fix it?

Yes, implement Range/Time Over for zsnes.

Hell. Ok, if you DMA transfer and you cross past the NMI trigger point, the NMI will execute once the DMA transfer finishes, regardless of where the DMA ends at. So if you're at x: 0, y: 224, and you DMA to x: 0, y: 227, or to x: 0, y: 63, or cross two frames and end up at x: 0, y: 230, it still ex...

Yes, exactly. How did you get 10 cycles from that, though? The shortest possible CPU cycle is 6, so that would mean FastROM would be 12 or more cycles minimum. Those are the results. If both are Fast (FastROM or IO), the delay is only 6 master cycles. If one is Fast and one is Slow, the delay is 8....

Ok, I ran some tests on NMI. The $4210 bit 7 seems to be set and cleared at exactly the same time as $4212 bit 7 (set = 0.5x, 225/240y ; clear = 0.5x, 0y). Your tests indicate that vblank clear/set is at 1.0x, so if that's right, NMI would also be 1.0x. Hrm... The only thing is, my tests indicate t...

pagefault knows this already (from IRC), but for the rest of you... The problem is that the game reads an open bus register, at $2000-$2001, and expects certain bits to be set in the result. It only works on the real SNES accidentally, while zsnes returns 0 for these unmapped registers and breaks th...

BTW, I'm only verifying the information because I feel the more times something is confirmed, the better. That's one of the major reasons I want you to verify everything. Man, you're good at this. I've always considered myself fairly proficient with writing optimized c++, but you always seem to do ...

No. VDA=0/VPA=0 for this cycle so you were right to assume it's always an I/O cycle. No read is performed here ever, and it is always 6 master cycles long. I wasn't sure about whether the read would go on the bus or not, it's good to know it doesn't. By the way, do you know if the latch counters ar...

Ok, that leads to a lot of questions. Let's say Y=$FF, LDA $4120,Y. Will the speculative read cycle end up costing 12 master cycles for $41xx region instead of 6 for $42xx region? Assuming VDP and VPA are both output as 0 for the cycle, I'm thinking that it'll only be 6 cycles no matter what... Wou...