I have read Anomie's Open Bus & Wrapping document, and I have a doubt about the Memory Data Register concept described in it. From what I understand, a CPU cannot know if a particular address is mapped or unmapped when reading data; it simply reads whatever value it senses on the data bus lines.
For buses which are driven entirely by CMOS parts, parasitic bus capacitance can maintain the voltages on bus lines when the bus is no longer driven (i.e. when the pins on the parts connected to the bus are tri-stated). I know the S-CPU/65C816 is a CMOS part, but I'm not sure if all the other components (S-PPU1, S-PPU2, etc.) connected to the SNES's buses are also CMOS. Assuming they are, I believe what's going on is that the CPU, when reading unmapped addresses, is merely reading the last value placed on the data bus maintained due to bus capacitance, since no component actively drove the data bus during the access period.
Please let me know if I'm misunderstanding anything.
Open Bus Comment
Moderator: ZSNES Mods
The "Memory Data Register" concept is a useful one for understanding behavior, and I agree that it's probably "implemented" using the parasitic capacitance of the data lines coupled with the high-impedance nature of CMOS inputs (not that it's intentional, hence my quotes). The same kind of thing occurs on the NES and I think Game Boy too.