> (these are the clock cycles they are referring to when denoting the
> "time" it takes for an instruction to complete).
> What byuu was commenting on is the added level of complexity, where
> the snes cpu clock cycle actually changes depending on what memory
> ranges it is accessing.
Ok - that makes sense now - that an instruction takes a variable number of clock cycles to complete. But the length of a clock doesn't change with the instruction, just the number of clock cycles to complete.
Or do you mean to say that the SNES actually slows down the rate at which PHI2 fires depending on the memory range being accessed?
> I may be misunderstanding again, but isn't that just table 6-7 in the pdf?
> Or do you mean something else?
I mean collecting the information in those tables into a reference that might look something kind of like
Code: Select all
ADC(d,x) Add Memory to Accumulator with Carry Direct Indexed Indirect
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|0|1|1|0|0|0|0|1| d |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
A = A + mem[mem[X + D + d]] + C
Sets status codes N, V, Z, C
The operand address is always in Bank 0.
Takes 6-8 cycles to complete